The invention relates to integrated circuits. More specifically, the invention relates to Chip on Tape packages.
At the heart of every integrated circuit is a small piece of semiconductor material known as a die. Rectangular or square in shape, the die is often no larger than a dime. Yet millions of transistors can be fabricated on it.
Surrounding the die is a mechanical package. The mechanical package includes conductors escaping from the die for connection to a printed circuit board. The package also includes a molding compound that protects the die and conductors from environmental "elements" such as moisture, dirt, stress, shock and vibration. Moisture, for example, can corrode the conductors. Stress, shock and vibration can damage the connections between the conductors and die. All of these elements can damage the die itself.
Many different types of mechanical packages are available. One type of mechanical package, known as a Chip on Tape (COT), is formed from a laminated tape and a molding compound. The laminated tape typically includes a thin layer of dielectric material and a leadframe, a layer of metal foil that is patterned by a photolithographic process into a plurality of leads or traces. The die is located in an opening in the tape and its bonding pads are bonded to leads extending into the opening. The opening is back-filled with the molding compound encapsulating the die and leadframe. Leads extending from the molding compound, known as pins, are adapted for connection to the printed wiring board. The COT is a thin, planar package having a high pin count.
In comparison to other mechanical packages such as plastic ball grid arrays (PBGAs) and Plastic Quad Flat Packs (PQFPs), the COT has a thinner profile and a higher pin count. These features make COTs very appealing to the computer industry as well as other industries where high pin count and low profile are extremely important.
As is often the case, a customer purchases a COT directly from a vendor and surface mounts the COT to a printed circuit board. During surface mounting, the pins of the COT are cut to size and soldered to the printed circuit board. After assembly, the printed circuit board is tested for functionality. If the printed circuit board fails the test, and the cause of failure is localized to the COT, the COT is removed from the board and returned to the vendor.
The COT is expensive enough to warrant electrical failure verification and failure analysis. If it is determined that the failure occurred because the die was defective, the customer is given a refund or credit. If, however, it is determined that the COT was damaged by the customer (for example, during mounting, programming or power up), the customer does not receive credit or a refund.
However, when the COT is returned to the vendor, the pins are usually mangled or destroyed. Such damage is caused by removing the COT from the board. Consequently, the COT is often in an untestable condition and cannot undergo electrical failure verification and failure analysis.
It is an objective of the present invention to be able to test a COT returned by a customer.